CPU Simulator is intended for students studying A-Level AQA Computer Science, who need to understand certain information on how a computer’s CPU functions. Specifically, the fetch-decode-execute cycle and how components of the processor change at each stage – depending on the code being run.
An interactive interface shows the components of the CPU, their contents, a description of what has changed in one clock cycle, an IDE to develop assembly code, an interface to view corresponding machine code, an interface to change preferences and more.
Components you can track:
• Address Bus
• Data Bus
• Clock
• Program Counter (PC)
• Current Instruction Register (CIR)
• Memory Address Register (MAR)
• Memory Buffer Register (MBR)
• 128 General Purpose Registers
• Arithmetic Logic Unit (ALU)
• Status Register
• 128 Data Memory Locations
• Instruction Memory
Options you can change:
• Run Speed (including stepped mode)
• Number Base
This is a document-based application which means that you can create and run an unlimited number of unique simulations, save and share them.
This app is primarily intended to help teach ‘4.7.3.2 The Fetch-Execute cycle and the role of registers within it’ of the AQA A-Level specification, using the Harvard Architecture.
An interactive interface shows the components of the CPU, their contents, a description of what has changed in one clock cycle, an IDE to develop assembly code, an interface to view corresponding machine code, an interface to change preferences and more.
Components you can track:
• Address Bus
• Data Bus
• Clock
• Program Counter (PC)
• Current Instruction Register (CIR)
• Memory Address Register (MAR)
• Memory Buffer Register (MBR)
• 128 General Purpose Registers
• Arithmetic Logic Unit (ALU)
• Status Register
• 128 Data Memory Locations
• Instruction Memory
Options you can change:
• Run Speed (including stepped mode)
• Number Base
This is a document-based application which means that you can create and run an unlimited number of unique simulations, save and share them.
This app is primarily intended to help teach ‘4.7.3.2 The Fetch-Execute cycle and the role of registers within it’ of the AQA A-Level specification, using the Harvard Architecture.
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